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TDA7449
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
1
FEATURES
INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES
Figure 1. Package
DIP20
SO20

ONE STEREO OUTPUT TREBLE, AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION
Table 1. Order Codes
Part Number TDA7449 TDA7449D Package DIP20 SO20

applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
2
DESCRIPTION
The TDA7449 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio Figure 2. Block Diagram
MUXOUTL 10 8 100K
TREBLE(L) 16
BIN(L) BOUT(L) 15 RB 14
L-IN1
L-IN2
9 100K G VOLUME TREBLE BASS SPKR ATT LEFT
5
LOUT
R-IN1
7 100K
0/30dB 2dB STEP
19 I2CBUS DECODER + LATCHES 20 18
SCL SDA DIG_GND
R-IN2
6 100K G VOLUME TREBLE BASS SPKR ATT RIGHT VREF
4
ROUT
2 INPUT MULTIPLEXER + GAIN 11 MUXOUTR 17 TREBLE(R) 12 SUPPLY RB 13 1 CREF 3
VS AGND
BIN(R) BOUT(R)
D98AU847A
June 2004
REV. 4 1/19
TDA7449
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Parameter Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Value 10.5 0 to 70 -55 to 150 Unit V C C
Figure 3. Pin Connection
CREF VS PGND ROUT LOUT R_IN2 R_IN1 L_IN1 L_IN2 MUXOUT(L)
1 2 3 4 5 6 7 8 9 10
D98AU848
20 19 18 17 16 15 14 13 12 11
SDA SCL DIG_GND TREBLE(R) TREBLE(L) BIN(L) BOUT(L) BOUT(R) BIN(R) MUXOUT(R)
Table 3. Thermal Data
Symbol Rth j-pin Parameter Thermal Resistance Junction- pins Value 85 Unit C/W
Table 4. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max Input Signal Handling Total Harmonic Distortion V = 0.1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Input Gain (2dB step) Volume Control (1dB step) Treble Control (2dB step) Bass Control (2dB step) Balance Control 1dB step Mute Attenuation 0 -47 -14 -14 -79 100 Parameter Min. 6 2 0.01 106 90 30 0 14 14 0 0.1 Typ. 9 Max. 10.2 Unit V VRMS % dB dB dB dB dB dB dB dB
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Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified) Symbol
SUPPLY VS IS SVR INPUT STAGE RIN VCL SIN Ginmin Ginman Gstep Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution THD = 0.3% The selected input is grounded through a 2.2 capacitor 2 80 -1 100 2.5 100 0 30 2 1 K Vrms dB dB dB dB Supply Voltage Supply Current Ripple Rejection 60 6 9 7 90 10.2 V mA dB
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VOLUME CONTROL CRANGE AVMAX ASTEP EA Control Range Max. Attenuation Step Resolution Attenuation Set Error AV = 0 to -24dB AV = -24 to -47dB ET Tracking Error AV = 0 to -24dB AV = -24 to -47dB VDC DC Step adjacent attenuation steps from 0dB to AV max Amute Mute Attenuation 80 45 45 0.5 -1.0 -1.5 47 47 1 0 0 0 0 0 0.5 100 49 49 1.5 1.0 1.5 1 2 3 dB dB dB dB dB dB dB mV mV dB
BASS CONTROL (1) Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12.0 1 18.75 +14.0 2 25 +16.0 3 31.25 dB dB K
TREBLE CONTROL (1) Gt TSTEP Control Range Step Resolution Max. Boost/cut +13.0 1 +14.0 2 +15.0 3 dB dB
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TDA7449
Table 5. Electrical Characteristcs (continued)
SPEAKER ATTENUATORS CRANGE SSTEP EA Control Range Step Resolution Attenuation Set Error AV = 0 to -20dB AV = -20 to -56dB VDC Amute DC Step Mute Attenuation adjacent attenuation steps 80 0.5 -1.5 -2 76 1 0 0 0 100 1.5 1.5 2 3 dB dB dB dB mV dB
AUDIO OUTPUTS VCLIP RL RO VDC GENERAL ENO Et Output Noise Total Tracking Error All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV = -24 to -47dB S/N SC d BUS INPUT VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 1 V V A V Signal to Noise Ratio Channel Separation Left/Right Distortion AV = 0; VI = 1VRMS ; All gains 0dB; VO = 1VRMS ; 80 5 0 0 106 100 0.01 0.08 15 1 2 V dB dB dB dB % Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2.1 2 10 40 3.8 70 2.6 VRMS K W V
Note: 1. The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does't reset the device. 2. BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
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TDA7449
Figure 4. P.C.Board (Referred to DIP20 package only)
Figure 5. Test Circuit
C9 5.6nF J5 IN1L J3 RCA 1 2 J4 3 4 5 CON3 IN1R J2 RCA 0/30dB 2dB STEP GND IN1L GND IN2L GND L-IN1 C3 0.47F L-IN2 C4 0.47F 9 100K G VOLUME TREBLE 8 100K MUXOUTL 10 TREBLE(L) 16
R2 2K 150nF 330nF
C7 BIN(L) 15 RB
C8 BOUT(L) 14 OUT_L 1 2 3 4 CON4 +9 V JP1 JUMPER OUT_R
J8
J9
OUT_L 5 LOUT BASS SPKR ATT LEFT OUT_ R
J10
18 I2CBUS DECODER + LATCHES 19 20
DIG_GND SCL SDA
1 2 3 4 CON4 J6
1 J1 2 3 4 CON
IN2R GND IN1R GND
R-IN2 C1 0.47F R-IN1 C2 0.47F
6 100K 7 VREF 100K 3 INPUT MULTIPLEXER + GAIN SUPPLY RB 11 MUXOUTR TREBLE(R) 17
BIN(R)
G
VOLUME
TREBLE
BASS
SPKR ATT RIGHT
4 ROUT
R3 30 AGND VS
C13 100nF +V8 +9V GND
C12 22F 1 2 CON2 J7
2
1 J5 2 3 4 CON4
MOUTL GND MOUTR GND
12 BOUT(R) C5 C6
13
1 CREF
C10 5.6nF
150nF R1
330nF 2K
C11 10F
D98AU849A
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TDA7449
3
APLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7449 audioprocessor provides 2 bands tones control. 3.1 Bass, Stages The Bass cell has an internal resistor Ri = 25K typical. Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.6 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal Fc, the gain Av at max. boost and the filter Q factor are computed as follows: Figure 6.
Ri internal IN C1 R2
D95AU313
OUT C2
1 FC = ----------------------------------------------------------------2 R1 R2 C 1 C2
R2C 2 + R2C1 + RiC1 AV = -----------------------------------------------------------R2 C1 + R2C2
R 1 R2 C1 C2 Q = ------------------------------------------------R 2C1 + R2C2
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
AV - 1 C1 = ----------------------------------------2 Fc Ri Q Q C1 C2 = ----------------------------2 AV - 1 - Q
2
AV - 1 - Q R2 = --------------------------------------------------------------------2 C1 Fc ( AV - 1 ) Q
2
3.2 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. 3.3 CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON.
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TDA7449
Figure 7. THD vs. frequency Figure 10. Bass response
Figure 8. THD vs. RLOAD
Figure 11. Treble response
Figure 9. Channel separation vs. frequency
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TDA7449
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7449 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 12, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig.13 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 14). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 12. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 13. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
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TDA7449
Figure 14. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
5
SOFTWARE SPECIFICATION
5.1 Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7449 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
Figure 15.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus The TDA7449 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. Figure 16.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
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TDA7449
6.2 Incremental Bus The TDA7449 receive a start conditions, the correct chip address, a subaddress with the B = 1 incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. Figure 17.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
Table 6. POWER ON RESET CONDITION
INPUT SELECTION INPUT GAIN VOLUME BASS TREBLE SPEAKER IN2 28dB MUTE 0dB 2dB MUTE
7
DATA BYTES
Address = 88 HEX (ADDR:OPEN). Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB SUBADDRESS D0 0 1 0 1 0 1 0 1 INPUT SELECT INPUT GAIN VOLUME NOT ALLOWED BASS TREBLE SPEAKER ATTENUATE "R" SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON'T CARE
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TDA7449
Table 8. INPUT SELECTION
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 LSB INPUT MULTIPLEXER D0 0 1 0 1 NOT ALLOWED NOT ALLOWED IN2 IN1
Table 9. INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GAIN = 0 to 30dB
LSB D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
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TDA7449
Table 10. VOLUME SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 X
VOLUME = 0 to 47dB/MUTE
LSB D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 1 X X X
MUTE
Table 11. BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
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TDA7449
Table 12. TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 TREBLE 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
Table 13. SPEAKER ATTENUATE SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATION 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
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TDA7449
Figure 18. PIN :1 Figure 21. PINS: 10, 11
VS
VS 20K
VS
VS 20A
CREF 20K
MUXOUT
GND
D96AU430
D96AU491
Figure 19. PINS: 4, 5
VS
Figure 22. PINS: 12, 15
VS 20A
ROUT LOUT 24
20A
25K BIN(L) BIN(R)
D96AU434
D98AU850
Figure 20. PINS: 6, 7, 8, 9
Figure 23. PINS: 13, 14,
VS 20A
VS 20A
IN
100K VREF
D96AU425
44K BOUT(L) BOUT(R)
D96AU429
14/19
TDA7449
Figure 24. PINS: 16, 17 Figure 26. PIN 20
VS 20A TREBLE(L) TREBLE(R) 50K
D96AU423
20A SDA
D96AU433
Figure 25. PIN: 19
20A SCL
D96AU424
15/19
TDA7449
Figure 27. DIP20 Mechanical Data & Package Dimensions
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.254 1.39
mm TYP. MAX. MIN. 0.010 1.65 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 0.055
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130
DIP20
0.053
16/19
TDA7449
Figure 28. SO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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TDA7449
Table 14. Revision History
Date March 2004 June 2004 Revision 3 4 Third Issue Modified the style-sheet in compliance with the last revision of the "Corporate Technical Pubblications Design Guide". Description of Changes
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TDA7449
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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